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page : ?#? rev. 0.11b : 2012.06.05 preliminary rev. 0.11b 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) features ? power supply ? 1.8 v for core (v dd ), 1.4 v to v dd for i/o (v ddq ) ? clock ? fast clock cycle time for high bandwidth ? two input clocks (k and /k) for precise ddr timing at clock rising edges only ? two output echo clocks (cq and /cq) simplify data capture in high-speed systems ? clock-stop capability with p s restart ? i/o ? common data input/output bus ? pipelined double data rate operation ? hstl i/o ? user programmable output impedance ? dll/pll circuitry for wide output data valid window and future frequency scaling ? data valid pin (qvld) to indicate valid data on the output ? function ? two-tick burst for low ddr transaction size ? internally self-timed write control ? simple control logic for easy depth expansion ? jtag 1149.1 compatible test access port ? package ? 165 fbga package (15 x 17 x 1.4 mm) description the r1q # a4436 is a 4,194,304-word by 36-bit and the r1q # a4418 is a 8,388,608-word by 18-bit synchronous double data rate static ram fabricated with advanced cmos technology using full cmos six-transistor memory cell. it integrates unique synchronous peripheral circuitry and a burst counter. all input registers are controlled by an input clock pair (k and /k) and are latched on the positive edge of k and /k. these products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. these products are packaged in 165-pin plastic fbga package. # = b: latency =2.5, w/o odt # = h: latency =2.0, w/o odt # = e: latency =2.5, w/ odt # = l: latency =2.0, w/ odt r1qba4436rbg / r1qba4418rbg / r1qba4409rbg r1qea4436rbg / r1qea4418rbg / r1qea4409rbg r1qha4436rbg / r1qha4418rbg / r1qha4409rbg r1qla4436rbg / r1qla4418rbg / r1qla4409rbg 144-mbit ddrii+ sram 2-word burst notes: 1. qdr rams and quad data rate rams comprise a new family of products developed by cypress semiconductor, idt, samsung, and renesas electronics corp. (qdr co-development team) 2. the specifications of this device are subject to change without notice. please contact your nearest renesas electronics sales office regarding specifications. 3. refer to " http://www.renesas.com/products/memory/fast_sram/qdr_sram/index.jsp " for the latest and detailed information. 4. descriptions about x9 parts in this datasheet are just for reference. r10ds0189ej0011 r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) part number definition common 0q %qoogpvu 0q %qoogpvu 0q %qoogpvu 4 4gpgucu/goqt[2tghkz # 8ff8 (tgswgpe[/*\ 3 3&4++$ =?
. =? &gpukv[/d (tgswgpe[/*\ 3 3&4++$
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. &gpukv[/d (tgswgpe[/ *\ 3 &&4++$5+1 =?
. &cvcykfvjdkv (tgswgpe[/*\ 3# 3&4++ $. =? &cvcykfvjdkv (tgswgpe[/*\ 3$ &&4++ $. &cvcykfvjdkv (tgswgpe[/*\ 3% &&4++ $. 4 uv)gpgtcvkqp (tgswgpe[/*\ 3& 3&4++ $.y1&6 =? # pf)gpgtcvkqp (tgswgpe[/*\ 3' &&4++ $.y1&6 $ tf)gpgtcvkqp (tgswgpe[/*\ 3( &&4++ $.y1&6 % vj)gpgtcvkqp (tgswgpe[/*\ 3) 3&4++ $. & vj)gpgtcvkqp 3* &&4++ $. ' vj)gpgtcvkqp 3, &&4++ $. ( vj)gpgtcvkqp 3- 3&4++ $.y1&6 $) 2-)$)#zoo 3. &&4++ $.y1&6 $# # 2d htgg cpf6tc[ 3/ &&4++ $.y1&6 $$ $ 2dhtggcpf6tc[ 30 3&4++ $. 6 2d htgg cpf6crg4ggn 32 3&4++ $.y1&6 5 2dhtggcpf6crg4ggn 0qvg =?$$wtuvngpivj
$$wtuvngpivj$$wtuvngpiv j =?.4gcf.cvgpe[
.4gcf.cvgpe[e[eng.e [eng.e[eng =?5+15grctcvg+1 =?1&61pfkgvgtokpcvkqp 0qvg 2cemcig/ctmkpi0cog 2d htgg rctvu/ctmkpi0cog2ctv0wodgt
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2$(
'zcorng43##4$)4 2d( 2d htgg rctvu
'zcorng 43##4$)42$(2dhtggrctvu 0qvg 2d htgg 4q*5%qornkcpeg.gxgn 2dhtgg4q*5%qornkcpeg.gxgn 0qvg 43#ugtkguuwrrqtvdqvj%qoogtekcncpf+pfwuvtkcnv gorgtcvwtgu d[+pfwuvtkcnvgorgtcvwtgrctvu 4 %qoogtekcnvgor 6ctcpig? +pfwuvtkcnvgor 6ctcpig? + `#`< qt0qpg 4gpgucukpvgtpcnwug 2-)$)#zoo part number definition table column no. 0 1 2 3 4 5 6 7 8 9 10 11 - 12 13 14 15 16 example r1q2a4418rbg- 40rb0 the above part number is just example for 144m qdrii b2 x18 250mhz, 15x17mm pkg, pb-free part. r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) hins= 00000.0000.0000.0000.0000 -- - 00000.0000.0000.0000.0000--- 11111.1111 .1111.1111.1111--- 144m notes: 1. " yy " represents the speed bin . "r1qaa4436rbg- 20 " can operate at 500 mhz(max) of frequency, for example. 2. the part which is not listed above is not supported, as of the day when this datasheet was issued, in spite of the existence of the part number or datasheet. 144m qdr/ddr sram lineup - renesas plans to support the parts listed below. 533 500 450 400 375 333 300 250 200 1.875 2.00 2.22 2.50 2.66 3.00 3.30 4.00 5.00 yy -19-20-22-25-27-30-33-40-50 2 x18 r1q 2 a44 18 r b g - yy 3 x36 r1q 2 a44 36 r b g - yy 5 x18 r1q 3 a44 18 r b g - yy 6 x36 r1q 3 a44 36 r b g - yy 8 x18 r1q 4 a44 18 r b g - yy 9 x36 r1q 4 a44 36 r b g - yy 11 x18 r1q 5 a44 18 r b g - yy 12 x36 r1q 5 a44 36 r b g - yy 14 x18 r1q 6 a44 18 r b g - yy 15 x36 r1q 6 a44 36 r b g - yy 20 x18 r1q a a44 18 r b g - yy 21 x36 r1q a a44 36 r b g - yy 23 x18 r1q b a44 18 r b g - yy 24 x36 r1q b a44 36 r b g - yy 26 x18 r1q c a44 18 r b g - yy 27 x36 r1q c a44 36 r b g - yy 32 x18 r1q d a44 18 r b g - yy 33 x36 r1q d a44 36 r b g - yy 35 x18 r1q e a44 18 r b g - yy 36 x36 r1q e a44 36 r b g - yy 38 x18 r1q f a44 18 r b g - yy 39 x36 r1q f a44 36 r b g - yy 41 x18 r1q n a44 18 r b g - yy 42 x36 r1q n a44 36 r b g - yy 44 x18 r1q g a44 18 r b g - yy 45 x36 r1q g a44 36 r b g - yy 47 x18 r1q h a44 18 r b g - yy 48 x36 r1q h a44 36 r b g - yy 50 x18 r1q j a44 18 r b g - yy 51 x36 r1q j a44 36 r b g - yy 53 x18 r1q p a44 18 r b g - yy 54 x36 r1q p a44 36 r b g - yy 56 x18 r1q k a44 18 r b g - yy 57 x36 r1q k a44 36 r b g - yy 59 x18 r1q l a44 18 r b g - yy 60 x36 r1q l a44 36 r b g - yy 62 x18 r1q m a44 18 r b g - yy 63 x36 r1q m a44 36 r b g - yy - : no plan status under development qdrii+ qdrii+ qdrii+ 2.5 no b4 b4 -40 -33 -33 -33 under development - -40 -33 -40 -22 -20 -22 -22 no product type burst length latency (cycle) odt organi- zation frequency (max) (mhz) cycle time (min) (ns) part number qdrii b2 1.5 no ddrii b2 b4 ddrii sio b2 -50 b4 -40 -40 -33 -19 ddrii+ b2 -19 -20 -20 b4 -19 -20 -22 2.5 yes -22 ddrii+ b2 -19 -20 b4 -20 -22 b4 -25 2.0 no b2 ddrii+ b2 -25 b4 -25 b4 -25 b2 ddrii+ b2 -25 2.0 yes qdrii+ under development b4 -25 -33 -19 -19 - - - - under development under development r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) r1q4a4418 (top) / r1qb(h)a4418 (mid) / r1qe(l)a4418 (bottom) 1234567891011 a /cq sa sa r-/w /bw1 /k sa /ld sa sa cq b nc dq9 nc sa nc k /bw0 sa nc nc dq8 c ncncncv ss sa sa0 nc nc sa v ss nc dq7 nc d nc nc dq10 v ss v ss v ss v ss v ss nc nc nc encncdq11v ddq v ss v ss v ss v ddq nc nc dq6 f nc dq12 nc v ddq v dd v ss v dd v ddq nc nc dq5 g nc nc dq13 v ddq v dd v ss v dd v ddq nc nc nc h/doffv ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j ncncncv ddq v dd v ss v dd v ddq nc dq4 nc k nc nc dq14 v ddq v dd v ss v dd v ddq nc nc dq3 l nc dq15 nc v ddq v ss v ss v ss v ddq nc nc dq2 m ncncncv ss v ss v ss v ss v ss nc dq1 nc n nc nc dq16 v ss sa sa sa v ss nc nc nc p nc nc dq17 sa sa c qvld qvld sa sa nc nc dq0 rtdotcksasasa /c nc odt sa sa sa tms tdi (top view) notes: 1. address expansion order for future higher density srams: 10a : 2a : 7a : 5b. 2. nc pins can be left floating or connected to 0v : v ddq . r1q4a4436 (top) / r1qb(h)a4436 (mid) / r1qe(l)a4436 (bottom) 1234567891011 a /cq sa sa r-/w /bw2 /k /bw1 /ld sa sa cq b nc dq27 dq18 sa /bw3 k /bw0 sa nc nc dq8 c nc nc dq28 v ss sa sa0 nc nc sa v ss nc dq17 dq7 d nc dq29 dq19 v ss v ss v ss v ss v ss nc nc dq16 e nc nc dq20 v ddq v ss v ss v ss v ddq nc dq15 dq6 f nc dq30 dq21 v ddq v dd v ss v dd v ddq nc nc dq5 g nc dq31 dq22 v ddq v dd v ss v dd v ddq nc nc dq14 h/doffv ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc dq32 v ddq v dd v ss v dd v ddq nc dq13 dq4 k nc nc dq23 v ddq v dd v ss v dd v ddq nc dq12 dq3 l nc dq33 dq24 v ddq v ss v ss v ss v ddq nc nc dq2 mncncdq34v ss v ss v ss v ss v ss nc dq11 dq1 n nc dq35 dq25 v ss sa sa sa v ss nc nc dq10 p nc nc dq26 sa sa c qvld qvld sa sa nc dq9 dq0 rtdotcksasasa /c nc odt sa sa sa tms tdi (top view) notes: 1. address expansion order for future higher density srams: 10a : 2a : 7a : 5b. 2. nc pins can be left floating or connected to 0v : v ddq . pin arrangement top 8 r1q4a4436 mid 8 r1qb(h)a4436 bottom 8 r1qe(l)a4436 r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) r1q4a4409 (top) / r1qb(h)a4409 (mid) / r1qe(l)a4409 (bottom) 1234567891011 a /cq sa sa r-/w nc /k sa /ld sa sa cq b ncncncsanc k /bwsancncdq4 c ncncncv ss sa sa sa v ss nc nc nc d ncncncv ss v ss v ss v ss v ss nc nc nc encncdq5v ddq v ss v ss v ss v ddq nc nc dq3 f ncncncv ddq v dd v ss v dd v ddq nc nc nc gncncdq6v ddq v dd v ss v dd v ddq nc nc nc h/doffv ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j ncncncv ddq v dd v ss v dd v ddq nc dq2 nc k ncncncv ddq v dd v ss v dd v ddq nc nc nc lncdq7ncv ddq v ss v ss v ss v ddq nc nc dq1 m ncncncv ss v ss v ss v ss v ss nc nc nc n ncncncv ss sa sa sa v ss nc nc nc p nc nc dq8 sa sa c qvld qvld sa sa nc nc dq0 rtdotcksasasa /c nc odt sa sa sa tms tdi (top view) notes: 1. address expansion order for future higher density srams: 10a : 2a : 7a : 5b. 2. nc pins can be left floating or connected to 0v : v ddq . 3. note that 6c is not sa0 and 7c is not sa1 in x9 product. thus u 9 product does not permit random start address on the two least significant address bits. sa0, sa1 = 0 at the start of each address. pin arrangement just reference r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) pin descriptions name i/o type descriptions notes sa x input synchronous address inputs: these inputs are registered and must meet the setup and hold times around the rising edge of k. all transactions operate on a burst-of-four words (two clock periods of bus activity). sa0 and sa1 are used as the lowest two address bits for burst read and burst write operations permitting a random burst start address on u 18 and u 36 of ddr ii (not ii+) devices. these inputs are ignored when device is deselected or once burst operation is in progress. /ld input synchronous load: this input is brought low when a bus cycle sequence is to be defined. this definition includes address and read / write direction. all transactions operate on a burst-of-four data (two clock periods of bus activity). r-/w input synchronous read / write input: when /ld is low, this input designates the access type (read when r-/w is high, write when r-/w is low) for the loaded address. r-/w must meet the setup and hold times around the rising edge of k. /bw x input synchronous byte writes: when low, these inputs cause their respective byte to be registered and written during write cycles. these signals are sampled on the same edge as the corresponding data and must meet setup and hold times around the rising edges of k and /k for each of the two rising edges comprising the write cycle. see byte write truth table for signal to data relationship. k, /k input input clock: this input clock pair registers address and control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of /k. /k is ideally 180 degrees out of phase with k. all synchronous inputs must meet setup and hold times around the clock rising edges. these balls cannot remain v ref level. c, /c (ii only) input output clock: this clock pair provides a user-controlled means of tuning device output data. the rising edge of /c is used as the output timing reference for the first and third output data. the rising edge of c is used as the output timing reference for second and fourth output data. ideally, /c is 180 degrees out of phase with c. c and /c may be tied high to force the use of k and /k as the output reference clocks instead of having to provide c and /c clocks. if tied high, c and /c must remain high and not to be toggled during device operation. these balls cannot remain v ref level. 1 /doff input dll/pll disable: when low, this input causes the dll/pll to be bypassed for stable, low frequency operation. tms tdi input ieee1149.1 test inputs: 1.8 v i/o levels. these balls may be left not connected if the jtag function is not used in the circuit. tck input ieee1149.1 clock input: 1.8 v i/o levels. this ball must be tied to v ss if the jtag function is not used in the circuit. notes: 1. r1q2, r1q3, r1q4, r1q5, r1q6 series have c and /c pins. r1qa, r1qb, r1qc, r1qd, r1qe, r1qf, r1qg, r1qh, r1qj, r1qk, r1ql, r1qm, r1qn, r1qp series do not have c, /c pins. in the series, k and /k are used as the output reference clocks instead of c and /c. therefore, hereafter, c and /c represent k and /k in this document. hins=00111.0011.0011.0011.0011 ---00111.0011.0011.0011.0011 --- 00111.0011.0011.0011.0011 ---ddr r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) name i/o type descriptions notes zq input output impedance matching input: this input is used to tune the device outputs to the system data bus impedance. dq and cq output impedance are set to 0.2 u rq, where rq is a resistor from this ball to ground. this ball can be connected directly to v ddq , which enables the minimum impedance mode. this ball cannot be connected directly to v ss or left unconnected. in odt (on die termination) enable devices, the odt termination values tracks the value of rq. the odt range is selected by odt control input. odt (ii+ only) input odt control: when low ; [option 1] low range mode is selected. the impedance range is between 52 : and 105 : (thevenin equivalent), which follows 0.3 u rq for 175 : ? rq ? 350 : . [option 2] odt is disabled. when high ; high range mode is selected. the impedance range is between 105 : and 150 : (thevenin equivalent), which follows 0.6 u rq for 175 : ? rq ? 250 : . when floating ; [option 1] high range mode is selected. [option 2] odt is disabled. 1 dq 0 to dq n input / output synchronous data i/os: input data must meet setup and hold times around the rising edges of k and /k. output data is synchronized to the respective c and /c, or to the respective k and /k if c and /c are tied high. the u 9 device uses dq0 ~ dq8. dq9 ~ dq35 should be treated as nc pin. the u 18 device uses dq0 ~ dq17. dq18 ~ dq35 should be treated as nc pin. the u 36 device uses dq0 ~ dq35. cq, /cq output synchronous echo clock outputs: the edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. these signals run freely and do not stop when dq tri- states. tdo output ieee 1149.1 test output: 1.8 v i/o level. qvld (ii+ only) output valid output indicator: the q valid indicates valid output data. qvld is edge aligned with cq and /cq. v dd supply power supply: 1.8 v nominal. see dc characteristics and operating conditions for range. 2 v ddq supply power supply: isolated output buffer supply. nominally 1.5 v. see dc characteristics and operating conditions for range. 2 v ss supply power supply: ground. 2 v ref hstl input reference voltage: nominally v ddq /2, but may be adjusted to improve system noise margin. provides a reference voltage for the hstl input buffers. nc no connect: these pins can be left floating or connected to 0v : v ddq . notes: 1. renesas status: option 1 = available, option 2 = possible. 2. all power supply and ground balls must be connected for proper operation of the device. r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) block diagram (r1qxa4436 / r1qxa4418 series, x=4 ) /ld /bwx k /k 72 /36 72 /36 22/23 36/18 36/18 dq 22/23 k c,/c or k,/k zq 2 cq, /cq 72 /36 4/2 r-/w sa0 sa0' memory array write register output register output select output buffer write driver sense amp mux burst logic output control logic sa0'' sa0''' sa /ld r-/w k address registry and logic data registry and logic /k notes 1. c and /c pins do not exist in ii+ series parts. c or k block diagram (r1qxa4436 / r1qxa4418 / r1qya4409 series, x=b,e,h,l, y=4,b,e,h,l) /ld /bwx k /k 72 /36 /18 21/22/23 36/18/9 36/18/9 dq 21/22/23 k c,/c or k,/k zq 2 cq, /cq memory array write register output register output select output buffer write driver sense amp mux 4/2/1 r-/w 72 /36 /18 72 /36 /18 sa /ld r-/w k address registry and logic data registry and logic /k notes 1. c and /c pins do not exist in ii+ series parts. c or k r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) hins= 00000.0000.0000.0000.0000 -- - 00000.0000.0000.0000.0000---11111.1111 .1111.1111.1111--- 144m status power up & unstable stage nop & set-up stage normal operation v dd set-up cycle v ddq v ref /doff 2. double clock mode k, /k fix high (=vddq) c, /c status power up & unstable stage nop & set-up stage normal operation v dd set-up cycle v ddq v ref /doff 1. single clock mode (c and /c pins fixed high) k, /k fix high (=vddq) general description power-up and initialization sequence -v dd must be stable before k, /k clocks are applied. - recommended voltage application sequence : v ss : v dd : v ddq & v ref : v in . (0 v to v dd , v ddq < 200 ms) - apply v ref after v ddq or at the same time as v ddq . - then execute either one of the following three sequences. 1. single clock mode (c and /c tied high) - drive /doff high (/doff can be tied high from the start). - then provide stable clocks (k, /k) for at least 20 us. 2. double clock mode (c and /c control outputs) ( ii series only ) - drive /doff high (/doff can be tied high from the start) - then provide stable clocks (k, /k , c, /c) for at least 20 us. 3. dll/pll off mode (/doff tied low) - in the "nop and setup stage", provide stable clocks (k, /k) for at least 20 us. r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) common dll/pll constraints 1. dll/pll uses k clock as its synchronizing input. the input should have low phase jitter which is specified as tkc var. 2. the lower end of the frequency at which the dll/pll can operate is 120 mhz. (please refer to ac characteristics table for detail.) 3. when the operating frequency is changed or /doff level is changed, setup cycles are required again. programmable output impedance 1. output buffer impedance can be programmed by terminating the zq ball to v ss through a precision resistor (rq). the value of rq is five times the output impedance desired. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is 250 : typical. the total external capacitance of zq ball must be less than 7.5 pf. r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) iip qvld (valid data indicator) (r1qa, r1qb, r1qc, r1qd, r1qe, r1qf, r1qg, r1qh, r1qj, r1qk, r1ql, r1qm r1qn, r1qp series) 1. qvld is provided on the qdr-ii+ and ddr-ii+ to simplify data capture on high speed systems. the q valid indicates valid output data. qvld is activated half cycle before the read data for the receiver to be ready for capturing the data. qvld is inactivated half cycle before the read finish for the receiver to stop capturing the data. qvld is edge aligned with cq and /cq. odt range odt control pin thevenin equivalent resistance (r thev ) unit notes option 1 option 2 - 6 low 0.3 u rq (odt disable) : 1, 4 high 0.6 u rq 0.6 u rq : 2, 5 floating 0.6 u rq (odt disable) : 3 notes: 1. allowable range of rq for option 1 to guarantee impedance matching a tolerance of r 20 % is 175 : ? rq ? 350 : . 2. allowable range of rq to guarantee impedance matching a tolerance of r 20 % is 175 : ? rq ? 250 : . 3. allowable range of rq for option 1 to guarantee impedance matching a tolerance of r 20 % is 175 : ? rq ? 250 : . 4. at option 1, odt control pin is connected to v ddq through 3.5 k : . therefore it is recommended to connect it to v ss through less than 100 : to make it low. 5. at option 2, odt control pin is connected to v ss through 3.5 k : . therefore it is recommended to connect it to v ddq through less than 100 : to make it high. 6. renesas status: option 1 = available, option 2 = possible. if you need devices with option 2, please contact renesas sales office. odt (on die termination) (r1qd, r1qe, r1qf, r1qk, r1ql, r1qm, r1qp series) 1. to reduce reflection which produces noise and lowers signal quality, the signals should be terminated, especially at high frequency. renesas offers odt on the input signals to qdr-ii+ and ddr-ii+ family of devices. (see the odt pin table) 2. in odt enable devices, the odt termination values tracks the value of rq. the odt range is selected by odt control input. (see the odt range table) 3. in ddr-ii+ devices having common i/o bus, odt is automatically enabled when the device inputs data and disabled when the device outputs data. 4. there is no difference in ac timing characte ristics between the srams with odt and srams without odt. 5. there is no increase in the i dd of srams with odt, however, there is an increase in the i ddq (current consumption from the i/o voltage supply) with odt. r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) iip thevenin termination output buffer sram with odt 2 u r thev 2 u r thev v ddq other lsi input buffer v ss zq v ss rq odt pin (r1qd, r1qe, r1qf, r1qk, r1ql, r1qm, r1qp series) pin name odt on/off timing notes option 1 option 2 3 odt pin = high odt pin = low or floating d 0 ~d n in separate i/o devices always on always off 1 dq 0 ~dq n in common i/o devices off: first read command + read latency - 0.5 cycle on: last read command + read latency + bl/2 cycle + 0.5 cycle (see below timing chart) always off 2 /bw x always on always off k, /k always on always off notes: 1. separate i/o devices are r1qd, r1qk, r1qp series. 2. common i/o devices are r1qe, r1qf, r1ql, r1qm series. 3. renesas status: option 1 = available, option 2 = possible. if you need devices with option 2, please contact renesas sales office. r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) iip nop command read (b2) ra k, /k status qa qb qb rc qc qc qd qd nop nop nop write (b2) we de de df df dg dg dh dh wg write (b2) qa dq dq odt disabled qj qi ri qi read (b2) enabled disabled enabled odt on/off timing chart for r1qe series (ddr ii+, burst length=2, read latency=2.5 cycle) read (b2) read (b2) read (b2) rb rd wf wh rj read (b2) write (b2) write (b2) nop command read (b4) ra k, /k status qa qa qa rc qc qc qc qc nop nop nop write (b4) we de de de de dg dg dg dg wg write (b4) qa dq dq odt disabled qi qi ri qi read (b4) enabled disabled enabled odt on/off timing chart for r1qf series (ddr ii+, burst length=4, read latency=2.5 cycle) - read (b4) - - - - nop command read (b2) ra k, /k status qa qb qb rc qc qc qd qd nop nop write (b2) we de de df df dg dg dh dh wg write (b2) qa dq dq odt disabled qj qi ri qi read (b2) enabled disabled enabled odt on/off timing chart for r1ql series (ddr ii+, burst length=2, read latency=2.0 cycle) read (b2) read (b2) read (b2) rb rd wf wh rj read (b2) write (b2) write (b2) qj read (b2) rk qk qk nop command read (b4) ra k, /k status qa qa qa rc qc qc qc qc nop nop write (b4) we de de de de dg dg dg dg wg write (b4) qa dq dq odt disabled qi qi ri qi read (b4) enabled disabled enabled odt on/off timing chart for r1qm series (ddr ii+, burst length=4, read latency=2.0 cycle) - read (b4) - - - - qi read (b4) rk qk qk notes 1. odt on/off switching timings are edge aligned with cq or /cq. r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) k truth table operation k /ld r-/w dq write cycle: load address, input write data on consecutive k and /k rising edges 9 ll data in input data d(a1) d(a2) input clock k(t+1) 9 /k(t+1) 9 read cycle: load address, output read data on consecutive c and /c rising edges 9 lh data out output data q(a1) q(a2) input clock for q rl *8 =1.5 /c(t+1) 9 c(t+2) 9 rl=2.0 c(t+2) 9 /c(t+2) 9 rl=2.5 /c(t+2) 9 c(t+3) 9 nop (no operation) 9 h u high-z standby (clock stopped) stopped uu previous state notes: 1. h: high level, l: low level, u : dont care, 9 : rising edge. 2. data inputs are registered at k and /k rising edges. data outputs are delivered at c and /c rising edges, except if c and /c are high, then data outputs are delivered at k and /k rising edges. 3. /ld and r-/w must meet setup/hold times around the rising edges (low to high) of k and are registered at the rising edge of k. 4. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 5. refer to state diagram and timing diagrams for clarification. 6. when clocks are stopped, the following cases are recommended; the case of k = low, /k = high, c = low and /c = high, or the case of k = high, /k = low, c = high and /c = low. this condition is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 7. a1 refers to the address input during a write or read cycle. a2 refers to the next internal burst address in accordance with the linear burst sequence. 8. rl = read latency (unit = cycle). burst sequence linear burst sequence table (r1q4aww36 / r1q4aww18 series ) sa0 sa0 notes external address 0 1 1st internal burst address 1 0 r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) byte write truth table ( x 36 ) operation k /k /bw0 /bw1 /bw2 /bw3 write d0 to d35 9 -llll - 9 llll write d0 to d8 9 - lhhh - 9 lhhh write d9 to d17 9 -hlhh - 9 hlhh write d18 to d26 9 -hhlh - 9 hhlh write d27 to d35 9 -hhhl - 9 hhhl write nothing 9 - hhhh - 9 hhhh notes: 1. h: high level, l: low level, 9 : rising edge. 2. assumes a write cycle was initiated. /bwx can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. common byte write truth table ( x 18 ) operation k /k /bw0 /bw1 write d0 to d17 9 -l l - 9 ll write d0 to d8 9 -l h - 9 lh write d9 to d17 9 -h l - 9 hl write nothing 9 -h h - 9 hh notes: 1. h: high level, l: low level, 9 : rising edge. 2. assumes a write cycle was initiated. /bwx can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. byte write truth table ( x 9 ) operation k /k /bw write d0 to d8 9 -l - 9 l write nothing 9 -h - 9 h notes: 1. h: high level, l: low level, 9 : rising edge. 2. assumes a write cycle was initiated. /bwx can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. just reference except r1q2a**09 series r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) notes: 1. sa0 is internally advanced in accordance with the burst order table. bus cycle is terminated at the end of this sequence (burst count = 2). 2. state machine control timing sequence is controlled by k. bus cycle state diagram nop write double count = count + 2 load new address count = 0 power up /ld = h supply voltage provided /ld = l r-/w = l /ld = l & count = 2 /ld = h & count = 2 read double count = count + 2 r-/w = h /ld = l & count = 2 /ld = h & count = 2 r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) absolute maximum ratings parameter symbol rating unit notes input voltage on any ball v in 0.5 to v dd + 0.5 (2.5 v max.) v1, 4 input/output voltage v i/o 0.5 to v ddq + 0.5 (2.5 v max.) v1, 4 core supply voltage v dd 0.5 to 2.5 v 1, 4 output supply voltage v ddq 0.5 to v dd v1, 4 junction temperature tj +125 (max) q c5 storage temperature t stg 55 to +125 q c notes: 1. all voltage is referenced to v ss . 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted the operation conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. these cmos memory circuits have been designed to meet the dc and ac specifications shown in the tables after thermal equilibrium has been established. 4. the following supply voltage application sequence is recommended: v ss , v dd , v ddq , v ref then v in . remember, according to the absolute maximum ratings table, v ddq is not to exceed 2.5 v, whatever the instantaneous value of v ddq . 5. some method of cooling or airflow should be considered in the system. (especially for high frequency or odt parts) common recommended dc operating conditions parameter symbol min typ max unit notes power supply voltage -- core v dd 1.7 1.8 1.9 v 1 power supply voltage -- i/o v ddq 1.4 1.5 v dd v1, 2 input reference voltage -- i/o v ref 0.68 0.75 0.95 v 3 input high voltage v ih (dc) v ref + 0.1 v ddq + 0.3 v 1, 4, 5 input low voltage v il (dc) 0.3 v ref 0.1 v 1, 4, 5 notes: 1. at power-up, v dd and v ddq are assumed to be a linear ramp from 0v to v dd (min.) or v ddq (min.) within 200ms. during this time v ddq < v dd and v ih < v ddq . during normal operation, v ddq must not exceed v dd . 2. please pay attention to tj not to exceed the temperature shown in the absolute maximum ratings table due to current from v ddq . 3. peak to peak ac component superimposed on v ref may not exceed 5% of v ref . 4. these are dc test criteria. the ac v ih / v il levels are defined separately to measure timing parameters. 5. overshoot: v ih (ac) d v ddq + 0.5 v for t d t khkh /2 undershoot: v il (ac) t 0.5 v for t d t khkh /2 during normal operation, v ih(dc) must not exceed v ddq and v il(dc) must not be lower than v ss . r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) hins= 00000.0000.0000.0000.0000 -- - 00000.0000.0000.0000.0000--- 11111.1111 .1111.1111.1111--- 144m dc characteristics (ta = 0 ~ +70 q c @ r1q*a*****bg-** r ** series, ta = -40 ~ +85 q c @ r1q*a*****bg-** i ** series) (v dd =1.8v r 0.1v, v ddq =1.5v, v ref = 0.75v) operating supply current (write / read) symbol = i dd . unit = ma. see notes 1, 2 and 3 in the page after next. notes: 1. " yy " represents the speed bin . "r1qaa4436rbg- 20 " can operate at 500 mhz(max) of frequency, for example. 533 500 450 400 375 333 300 250 200 1.875 2.00 2.22 2.50 2.66 3.00 3.30 4.00 5.00 yy -19 -20 -22 -25 -27 -30 -33 -40 -50 2 x18 r1q 2 a44 18 r b g - yy tbd tbd 3 x36 r1q 2 a44 36 r b g - yy tbd tbd 5 x18 r1q 3 a44 18 r b g - yy tb d tb d 6 x36 r1q 3 a44 36 r b g - yy tb d tb d 8 x18 r1q 4 a44 18 r b g - yy tb d tb d 9 x36 r1q 4 a44 36 r b g - yy tb d tb d 11 x18 r1q 5 a44 18 r b g - yy tb d tb d 12 x36 r1q 5 a44 36 r b g - yy tb d tb d 14 x18 r1q 6 a44 18 r b g - yy tb d tb d 15 x36 r1q 6 a44 36 r b g - yy tb d tb d 20 x18 r1q a a44 18 r b g - yy tb d tb d tb d 21 x36 r1q a a44 36 r b g - yy tb d tb d tb d 23 x18 r1q b a44 18 r b g - yy tb d tb d tb d 24 x36 r1q b a44 36 r b g - yy tb d tb d tb d 26 x18 r1q c a44 18 r b g - yy tb d tb d tb d 27 x36 r1q c a44 36 r b g - yy tb d tb d tb d 32 x18 r1q d a44 18 r b g - yy tb d tb d tb d 33 x36 r1q d a44 36 r b g - yy tb d tb d tb d 35 x18 r1q e a44 18 r b g - yy tb d tb d tb d 36 x36 r1q e a44 36 r b g - yy tb d tb d tb d 38 x18 r1q f a44 18 r b g - yy tb d tb d tb d 39 x36 r1q f a44 36 r b g - yy tb d tb d tb d 41 x18 r1q n a44 18 r b g - yy tb d 42 x36 r1q n a44 36 r b g - yy tb d 44 x18 r1q g a44 18 r b g - yy tb d 45 x36 r1q g a44 36 r b g - yy tb d 47 x18 r1q h a44 18 r b g - yy tb d 48 x36 r1q h a44 36 r b g - yy tb d 50 x18 r1q j a44 18 r b g - yy tb d 51 x36 r1q j a44 36 r b g - yy tb d 53 x18 r1q p a44 18 r b g - yy tb d 54 x36 r1q p a44 36 r b g - yy tb d 56 x18 r1q k a44 18 r b g - yy tb d 57 x36 r1q k a44 36 r b g - yy tb d 59 x18 r1q l a44 18 r b g - yy tb d 60 x36 r1q l a44 36 r b g - yy tb d 62 x18 r1q m a44 18 r b g - yy tb d 63 x36 r1q m a44 36 r b g - yy tb d qdrii+ b2 2.0 yes b4 ddrii+ b2 b4 no ddrii+ b2 b4 b2 b4 b2 2.5 2.0 b4 yes ddrii+ qdrii+ b4 qdrii+ b4 2.5 no ddrii+ b4 b2 qdrii+ qdrii b2 1.5 no b4 ddrii b2 b4 ddrii sio b2 odt organi- zation frequency (max) (mhz) cycle time (min) (ns) part number no product type burst length latency (cycle) r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) hins= 00000.0000.0000.0000.0000 -- - 00000.0000.0000.0000.0000--- 11111.1111 .1111.1111.1111--- 144m standby supply current (nop) symbol = i sb1 . unit = ma. see notes 2, 4 and 5 in the next page. notes: 1. " yy " represents the speed bin . "r1qaa4436rbg- 20 " can operate at 500 mhz(max) of frequency, for example. 533 500 450 400 375 333 300 250 200 1.875 2.00 2.22 2.50 2.66 3.00 3.30 4.00 5.00 yy -19 -20 -22 -25 -27 -30 -33 -40 -50 2 x18 r1q 2 a44 18 r b g - yy tbd tbd 3 x36 r1q 2 a44 36 r b g - yy tbd tbd 5 x18 r1q 3 a44 18 r b g - yy tb d tb d 6 x36 r1q 3 a44 36 r b g - yy tb d tb d 8 x18 r1q 4 a44 18 r b g - yy tb d tb d 9 x36 r1q 4 a44 36 r b g - yy tb d tb d 11 x18 r1q 5 a44 18 r b g - yy tb d tb d 12 x36 r1q 5 a44 36 r b g - yy tb d tb d 14 x18 r1q 6 a44 18 r b g - yy tb d tb d 15 x36 r1q 6 a44 36 r b g - yy tb d tb d 20 x18 r1q a a44 18 r b g - yy tb d tb d tb d 21 x36 r1q a a44 36 r b g - yy tb d tb d tb d 23 x18 r1q b a44 18 r b g - yy tb d tb d tb d 24 x36 r1q b a44 36 r b g - yy tb d tb d tb d 26 x18 r1q c a44 18 r b g - yy tb d tb d tb d 27 x36 r1q c a44 36 r b g - yy tb d tb d tb d 32 x18 r1q d a44 18 r b g - yy tb d tb d tb d 33 x36 r1q d a44 36 r b g - yy tb d tb d tb d 35 x18 r1q e a44 18 r b g - yy tb d tb d tb d 36 x36 r1q e a44 36 r b g - yy tb d tb d tb d 38 x18 r1q f a44 18 r b g - yy tb d tb d tb d 39 x36 r1q f a44 36 r b g - yy tb d tb d tb d 41 x18 r1q n a44 18 r b g - yy tb d 42 x36 r1q n a44 36 r b g - yy tb d 44 x18 r1q g a44 18 r b g - yy tb d 45 x36 r1q g a44 36 r b g - yy tb d 47 x18 r1q h a44 18 r b g - yy tb d 48 x36 r1q h a44 36 r b g - yy tb d 50 x18 r1q j a44 18 r b g - yy tb d 51 x36 r1q j a44 36 r b g - yy tb d 53 x18 r1q p a44 18 r b g - yy tb d 54 x36 r1q p a44 36 r b g - yy tb d 56 x18 r1q k a44 18 r b g - yy tb d 57 x36 r1q k a44 36 r b g - yy tb d 59 x18 r1q l a44 18 r b g - yy tb d 60 x36 r1q l a44 36 r b g - yy tb d 62 x18 r1q m a44 18 r b g - yy tb d 63 x36 r1q m a44 36 r b g - yy tb d qdrii+ b2 2.0 yes b4 ddrii+ b2 b4 no ddrii+ b2 b4 b2 b4 b2 2.5 2.0 b4 yes ddrii+ qdrii+ b4 qdrii+ b4 2.5 no ddrii+ b4 b2 qdrii+ qdrii b2 1.5 no b4 ddrii b2 b4 ddrii sio b2 odt organi- zation frequency (max) (mhz) cycle time (min) (ns) part number no product type burst length latency (cycle) r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) common leakage currents & output voltage parameter symbol min max unit test condition notes input leakage current i li 22 p a10 output leakage current i lo 55 p a11 output high voltage v oh (low) v ddq 0.2 v ddq v|i oh | d 0.1 ma 8, 9 v oh v ddq /2 0.12 v ddq /2 0.12 v note 6 8, 9 output low voltage v ol (low) v ss 0.2 v i ol d 0.1 ma 8, 9 v ol v ddq /2 0.12 v ddq /2 0.12 v note 7 8, 9 notes: 1. all inputs (except zq, v ref ) are held at either v ih or v il . 2. i out = 0 ma. v dd = v dd max, t khkh = t khkh min. 3. operating supply currents (i dd ) are measured at 100% bus utilization. i dd of qdr family is current of device with 100% write and 100% read cycle. i dd of ddr family is current of device with 100% write cycle (if i dd (write) > i dd (read)) or 100% read cycle (if i dd (write) < i dd (read)). 4. all address / data inputs are static at either v in > v ih or v in < v il . 5. reference value. (condition = nop currents are valid when entering nop after all pending read and write cycles are completed. ) 6. outputs are impedance-controlled. |i oh | = (v ddq /2)/(rq/5) for values of 175 :d rq d 350 : . 7. outputs are impedance-controlled. i ol = (v ddq /2)/(rq/5) for values of 175 :d rq d 350 : . 8. ac load current is higher than the shown dc values. ac i/o curves are available upon request. 9. hstl outputs meet jedec hstl class i and class ii standards. 10. 0 d v in d v ddq for all input balls (except v ref , zq, tck, tms, tdi ball). if r1qd, r1qe, r1qf, r1qk, r1ql, r1qm, r1qp series, balls with odt do not follow this spec. 11. 0 d v out d v ddq (except tdo ball), output disabled. r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) hins=00000.0000.0000.0000.0000---00000.0000.0000.0000.0000--- 11111.1111.1111.1111.1111---144m ac test conditions input waveform (rise/fall time d 0.3 ns) 1.25v 0.25v 0.75v 0.75v test points output waveform v ddq /2 test points v ddq /2 capacitance (ta = +25 q c, frequency = 1.0mhz, v dd =1.8v, v ddq =1.5v) parameter symbol min typ max unit test condition notes input capacitance (sa, /r, /w, /bw, d (separate) ) c in 45pf v in = 0 v 1, 2 clock input capacitance (k, /k, c, /c) c clk 45pf v clk = 0 v 1, 2 output capacitance (q (separate) , dq (common) , cq, /cq) c i/o 56pf v i/o = 0 v 1, 2 notes: 1. these parameters are sampled and not 100% tested. 2. except jtag (tck, tms, tdi, tdo) pins. thermal resistance parameter symbol airflow typ unit test condition notes junction to ambient ja 1 m/s 9.7 q c/w eia/jedec jesd51 1 junction to case jc -4.4 notes: 1. these parameters are calculated under the condition. these are reference values. 2. tj = ta + ja ? pd tj = tc + jc ? pd where tj : junction temperature when the device has achieved a steady-state after application of pd ( r c) ta : ambient temperature ( r c) tc : temperature of external surface of the package or case ( r c) ja : thermal resistance from junction-to-ambient ( r c/w) jc : thermal resistance from junction-to-case (package) ( r c/w) pd : power dissipation that produced change in junction temperature (w) (cf.jesd51-2a) r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) common ac operating conditions parameter symbol min typ max unit notes input high voltage v ih (ac) v ref + 0.2 v 1, 2, 3, 4 input low voltage v il (ac) v ref C 0.2 v 1, 2, 3, 4 notes: 1. all voltages referenced to v ss (gnd). during normal operation, v ddq must not exceed v dd . 2. these conditions are for ac functions only, not for ac parameter test. 3. overshoot: v ih (ac) d v ddq + 0.5 v for t d t khkh /2 undershoot: v il (ac) t 0.5 v for t d t khkh /2 control input signals may not have pulse widths less than t khkl (min) or operate at cycle rates less than t khkh (min). 4. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through the target ac level, v il (ac) or v ih (ac) . b. reach at least the target ac level. c. after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc) . output load conditions output load and voltage conditions 50 : zq q v ref 250 : z 0 = 50 : sram v ddq / 2 = 0.75v v ddq / 2 = 0.75v v dd v ddq v ss 1.8v r 0.1v 1.5v r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) hins= 00000.0000.0000.0000.0000 -- - 00000.0000.0000.0000.0000 --- 00000.0111.0111.0000.0000 ---rl=2.5 ac characteristics ( read latency = 2.5 cycle ) (ta = 0 ~ +70 q c @ r1q*a*****bg-** r ** series) (ta = -40 ~ +85 q c @ r1q*a*****bg-** i ** series) (v dd =1.8v r 0.1v, v ddq =1.5v, v ref = 0.75v) parameter symbol -19 -20 -22 -25 -27 -30 unit notes min max min max min max min max min max min max clock average clock cycle time (k, /k) t khkh 1.875 4.00 2.00 4.00 2.22 4.00 2.50 4.00 2.66 4.00 3.00 4.00 ns clock high time (k, /k) t khkl 0.40 0.40 0.40 0.40 0.40 0.40 cy- cle clock low time (k, /k) t klkh 0.40 0.40 0.40 0.40 0.40 0.40 cy- cle clock to /clock (k to /k) t kh/kh 0.425 0.425 0.425 0.425 0.425 0.425 cy- cle /clock to clock (/k to k) t /khkh 0.425 0.425 0.425 0.425 0.425 0.425 cy- cle dll/pll timing clock phase jitter (k, /k) t kc var 0.15 0.15 0.15 0.20 0.20 0.20 ns 3 lock time (k) t kc lock 20 20 20 20 20 20 us 2 k static to dll/pll reset t kc reset 30 30 30 30 30 30 ns 7 output times k, /k high to output valid t chqv 0.45 0.45 0.45 0.45 0.45 0.45 ns k, /k high to output hold t chqx 0.45 0.45 0.45 0.45 0.45 0.45 ns k, /k high to echo clock valid t chcqv 0.45 0.45 0.45 0.45 0.45 0.45 ns k, /k high to echo clock hold t chcqx 0.45 0.45 0.45 0.45 0.45 0.45 ns cq, /cq high to output valid t cqhqv 0.15 0.15 0.15 0.20 0.20 0.20 ns 4, 7 cq, /cq high to output hold t cqhqx 0.15 0.15 0.15 0.20 0.20 0.20 ns 4, 7 k, /k high to output high-z t chqz 0.45 0.45 0.45 0.45 0.45 0.45 ns 5, 6 k, /k high to output low-z t chqx1 0.45 0.45 0.45 0.45 0.45 0.45 ns 5 cq high to qvld valid t qvld 0.15 0.15 0.15 0.15 0.15 0.15 0.20 0.20 0.20 0.20 0.20 0.20 ns 7 r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) hins= 00000.0000.0000.0000.0000 -- - 00000.0000.0000.0000.0000--- 00000.0111.0111.0000.0000 ---rl=2.5 parameter symbol -19 -20 -22 -25 -27 -30 unit notes min max min max min max min max min max min max setup times address valid to k rising edge t avkh (qdrii+ b2) ns 1, 8 t avkh (qdrii+ b4 & ddrii+) 0.30 0.33 0.40 0.40 0.40 0.40 control inputs valid to k rising edge t ivkh (qdrii+ b2) ns 1, 8 t ivkh (qdrii+ b4 & ddrii+) 0.30 0.33 0.40 0.40 0.40 0.40 data-in valid to k, /k rising edge t dvkh 0.20 0.22 0.25 0.28 0.28 0.28 ns 1, 9 hold times k rising edge to address hold t khax (qdrii+ b2) ns 1, 8 t khax (qdrii+ b4 & ddrii+) 0.30 0.33 0.40 0.40 0.40 0.40 k rising edge to control inputs hold t khix (qdrii+ b2) ns 1, 8 t khix (qdrii+ b4 & ddrii+) 0.30 0.33 0.40 0.40 0.40 0.40 k, /k rising edge to data-in hold t khdx 0.20 0.22 0.25 0.28 0.28 0.28 ns 1, 9 notes: 1. this is a synchronous device. all addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 2. v dd and v ddq slew rate must be less than 0.1 v dc per 50 ns for dll/pll lock retention. dll/pll lock time begins once v dd , v ddq and input clock are stable. it is recommended that the device is kept inactive during these cycles. 3. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. echo clock is very tightly controlled to data valid / data hold. by design, there is a r 0.1 ns variation from echo clock to data. the datasheet parameters reflect tester guardbands and test setup variations. 5. transitions are measured r 100 mv from steady-state voltage. 6. at any given voltage and temperature t chqz is less than t chqx1 and t chqv . 7. these parameters are sampled. 8. t avkh , t ivkh , t khax , t khix spec is determined by the actual frequency regardless of part number (marking name). the following is the spec for the actual frequency. 0.30 ns for ? 533mhz & >500mhz 0.33 ns for ? 500mhz & >450mhz 0.40 ns for ? 450mhz & ? 250mhz 9. t dvkh , t khdx spec is determined by the actual frequency regardless of part number (marking name). the following is the spec for the actual frequency. 0.20 ns for ? 533mhz & >500mhz 0.22 ns for ? 500mhz & >450mhz 0.25 ns for ? 450mhz & >400mhz 0.28 ns for ? 400mhz & ? 250mhz remarks: 1. test conditions as specified with the output loading as shown in ac test conditions unless otherwise noted. 2. control input signals may not be operated with pulse widths less than t khkl (min). 3. v ddq is +1.5 v dc. v ref is +0.75 v dc. 4. control signals are /r, /w (qdr series), /ld, r-/w (ddr series), /bw, /bw0, /bw1, /bw2 and /bw3. setup and hold times of /bwx signals must be the same as those of data-in signals. r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) hins=00000.0010.0010.0000.0000 -- - 00000.0010.0010.0000.0000 ---00000.0010.0010.0000.0000--- r1qb_rl=2.5 r tqvld -tqvld tqvld -tqvld 1 2 3 4 5 6 7 8 9 10 11 12 13 k, /k nop read (burst of 2) read (burst of 2) write (burst of 2) nop nop tkhax tavkh /ld:r-/w sa tkhkh tkhkl tklkh tkh/kh t/khkh k /k tkhix tivkh write (burst of 2) read (burst of 2) a0 00 00 01 01 1x 1x 1x a2 a6 a4 notes: 1. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, etc. 2. outputs are disabled (high-z) n clock cycle after the last read cycle. here, n = read latency + burst length u 0.5. 3. in this example, if address a8 = a7, then data q80 = d70, q81 = d71, etc. write data is forwarded immediately as read result s. 4. to control read and write operations, /bw signals must operate at the same timing as data-in signals . 5. the third nop cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to p revent bus contention. read (burst of 2) read (burst of 2) write (burst of 2) write (burst of 2) 01 01 00 00 01 a1 a3 a5 a8 a7 tchcqv -tchcqx tchcqv -tchcqx q00 qx1 q01 q10 q11 q20 q21 q30 tchqv -tchqx tchqv -tchqx tcqhqv -tcqhqx -tchqx1 q31 tchqz qx0 qx1 dq cq /cq qvld d40 d41 d50 d51 d60 d61 d70 d71 tkhdx tdvkh tkhdx tdvkh nop timing waveforms (ddrii+, b2, read latency = 2.5 cycle) r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) jtag specification these products support a limited set of jtag functions as in ieee standard 1149.1. disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude mid level inputs. tdi and tms are internally pulled up and may be unconnected, or may be connected to vdd through a pull up resistor. tdo should be left unconnected. test access port (tap) pins symbol i/o pin assignments description notes tck 2r test clock input. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms 10r test mode select. this is the command input for the tap controller state machine. tdi 11r test data input. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction. tdo 1r test data output. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. notes: the device does not have trst (tap reset). the test-logic reset state is entered while tms is held high for five rising edges of tck. the tap controller state is also reset on sram power-up. common r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) tap dc operating characteristics (ta = 0 ~ +70 q c @ r1q*a*****bg-** r ** series) (ta = -40 ~ +85 q c @ r1q*a*****bg-** i ** series) (v dd =1.8v r 0.1v) parameter symbol min typ max unit notes input high voltage v ih +1.3 v dd + 0.3 v input low voltage v il 0.3 0.5 v input leakage current i li 5.0 5.0 p a0 v d v in d v dd output leakage current i lo 5.0 5.0 p a 0 v d v in d v dd , output disabled output low voltage v ol1 0.2 v i olc = 100 p a v ol2 0.4 v i olt = 2 ma output high voltage v oh1 1.6 v|i ohc | = 100 p a v oh2 1.4 v|i oht | = 2 ma notes: 1. all voltages referenced to v ss (gnd). 2. at power-up, v dd and v ddq are assumed to be a linear ramp from 0v to v dd (min.) or v ddq (min.) within 200ms. during this time v ddq < v dd and v ih < v ddq . during normal operation, v ddq must not exceed v dd . common r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) tap ac test conditions parameter symbol conditions unit notes input timing measurement reference levels v ref 0.9 v input pulse levels v il , v ih 0 to 1.8 v input rise/fall time tr, tf d 1.0 ns output timing measurement reference levels 0.9 v test load termination supply voltage (v tt ) 0.9 v output load see figures common external load at test 50 : v tt = 0.9v tdo z 0 = 50 : dut 20pf 1.8v input waveform 0v 0.9v 0.9v test points output waveform 0.9v test points 0.9v output load condition r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) tap ac operating characteristics (ta = 0 ~ +70 q c @ r1q*a*****bg-** r ** series) (ta = -40 ~ +85 q c @ r1q*a*****bg-** i ** series) (v dd =1.8v r 0.1v) parameter symbol min typ max unit notes test clock (tck) cycle time t thth 50 ns tck high pulse width t thtl 20 ns tck low pulse width t tlth 20 ns test mode select (tms) setup t mvth 5 ns tms hold t thmx 5 ns capture setup t cs 5 ns 1 capture hold t ch 5 ns 1 tdi valid to tck high t dvth 5 ns tck high to tdi invalid t thdx 5 ns tck low to tdo unknown t tlqx 0 ns tck low to tdo valid t tlqv 10 ns notes: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure pad data capture. common r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) test access port registers register name length symbol notes instruction register 3 bits ir [2:0] bypass register 1 bit bp id register 32 bits id [31:0] boundary scan register 109 bits bs [109:1] tap controller timing diagram tck tdi tms tdo pi (sram) tthtl tthth ttlth tmvth tthmx tdvth tthdx tcs tch ttlqv ttlqx common r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) tap controller instruction set ir2 ir1 ir0 instruction description notes 0 0 0 extest the extest instruction allows circuitry external to the component package to be tested. boundary scan register cells at output balls are used to apply test vectors, while those at input balls capture test results. typically, the first test vector to be applied using the extest instruction will be shifted into the boundary scan register using the preload instruction. thus, during the update-ir state of extest, the output driver is turned on and the preload data is driven onto the output balls. 1, 2, 3, 5 0 0 1 idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo balls in shift- dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. 0 1 0 sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (high-z), moving the tap controller into the capture-dr state loads the data in the rams input into the boundary scan register, and the boundary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. 3, 4, 5 0 1 1 reserved the reserved instructions are not implemented but are reserved for future use. do not use these instructions. 100 sample (/preload) when the sample instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. because the ram clock(s) are independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable input will not harm the device, repeatable results cannot be expected. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo balls. 3, 5 1 0 1 reserved - 1 1 0 reserved - 1 1 1 bypass the bypass instruction is loaded in the instruction register when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing of other dev ices in the scan path. notes: 1. data in output register is not guaranteed if extest instruction is loaded. 2. after performing extest, power-up conditions are required in order to return part to normal operation. 3. ram input signals must be stabilized for long enough to meet the taps input data capture setup plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. 4. clock recovery initialization cycles are required after boundary scan. 5. for r1qd, r1qe, r1qf, r1qk, r1ql, r1qm, r1qp series, odt is disabled in extest, sample-z or sample mode. common r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) boundary scan order bit # ball id signal names bit # ball id signal names x9 x18 x36 x9 x18 x36 16r /c or nc or odt /c or nc or odt /c or nc or odt 36 10e nc nc dq15 26p c or qvld c or qvld c or qvld 37 10d nc nc nc 36nsasasa389encncnc 47psasasa3910cncdq7dq17 5 7n sa sa sa 40 11d nc nc dq16 67rsasasa419cncncnc 78rsasasa429dncncnc 88psasasa4311bdq4dq8dq8 9 9r sa sa sa 44 11c nc nc dq7 10 11p dq0 dq0 dq0 45 9b nc nc nc 11 10p nc nc dq9 46 10b nc nc nc 12 10n nc nc nc 47 11a cq cq cq 13 9p nc nc nc 48 10a sa sa sa 14 10m nc dq1 dq11 49 9a sa sa sa 1511nncncdq10508bsasasa 16 9m nc nc nc 51 7c sa sa sa 17 9n nc nc nc 52 6c sa sa0 or nc sa0 or nc 18 11l dq1 dq2 dq2 53 8a /ld /ld /ld 19 11m nc nc dq1 54 7a sa sa /bw1 20 9l nc nc nc 55 7b /bw /bw0 /bw0 21 10l nc nc nc 56 6b k k k 2211kncdq3dq3576a/k/k/k 23 10k nc nc dq12 58 5b nc nc /bw3 24 9j nc nc nc 59 5a nc /bw1 /bw2 25 9k nc nc nc 60 4a r-/w r-/w r-/w 26 10j dq2 dq4 dq13 61 5c sa sa sa 27 11j nc nc dq4 62 4b sa sa sa 2811hzqzqzq633asasasa 29 10g nc nc nc 64 2a sa sa sa 30 9g nc nc nc 65 1a /cq /cq /cq 3111fncdq5dq5662bncdq9dq27 3211gncncdq14673bncncdq18 33 9f nc nc nc 68 1c nc nc nc 34 10f nc nc nc 69 1b nc nc nc 35 11e dq3 dq6 dq6 70 3d nc dq10 dq19 r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) boundary scan order bit # ball id signal names bit # ball id signal names x9 x18 x36 x9 x18 x36 71 3c nc nc dq28 91 2l dq7 dq15 dq33 72 1d nc nc nc 92 3l nc nc dq24 73 2c nc nc nc 93 1m nc nc nc 74 3e dq5 dq11 dq20 94 1l nc nc nc 75 2d nc nc dq29 95 3n nc dq16 dq25 76 2e nc nc nc 96 3m nc nc dq34 77 1e nc nc nc 97 1n nc nc nc 78 2f nc dq12 dq30 98 2m nc nc nc 79 3f nc nc dq21 99 3p dq8 dq17 dq26 80 1g nc nc nc 100 2n nc nc dq35 81 1f nc nc nc 101 2p nc nc nc 82 3g dq6 dq13 dq22 102 1p nc nc nc 83 2g nc nc dq31 103 3r sa sa sa 84 1h /doff /doff /doff 104 4r sa sa sa 85 1j nc nc nc 105 4p sa sa sa 86 2j nc nc nc 106 5p sa sa sa 87 3k nc dq14 dq23 107 5n sa sa sa 88 3j nc nc dq32 108 5r sa sa sa 89 2k nc nc nc 109 inter- nal inter- nal inter- nal 90 1k nc nc nc notes: in boundary scan mode, 1. clock balls (k, /k, c, /c) are referenced to each other and must be at opposite logic levels for reliable operation. 2. cq and /cq data are synchronized to the respective c and /c (except extest, sample-z). 3. if c and /c tied high, cq is generated with respect to k and /cq is generated with respect to /k (except extest, sample-z). r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) tap controller state diagram notes: the value adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. no matter what the original state of the controller, it will enter test-logic-reset when tms is held high for at least five rising edges of tck. select ir scan capture ir shift ir exit1 ir pause ir exit2 ir update ir 0 0 1 0 1 1 0 1 0 0 1 select dr scan capture dr shift dr exit1 dr pause dr exit2 dr update dr 0 0 1 0 1 1 0 1 0 0 1 run test/idle 0 10 1 test logic reset 1 1 0 0 11 common id register b? b? # 313029282726252423222120191817161514131211109876543210 symbol rrr0cmmmaww01qqqbos0010001000111 rrr q 000 0 001 1 010 q 011 0 1 cq 00 11 mmm b 010 0 011 1 101 o 110 0 a1 0s 10 ww 1 00 10 11 :: density = 72mb density = 36mb latency=1.5 (@ii), latency=2.0 (@ii+) latency=2.5 (@ii+) burst length = 2 word burst revis on 0 ii (q dr-ii, ddr-ii) revison 1 revison 2 revison 3 start bit (0) g - revision number (31 :29) type number (28 : 12) x36 36m&72m w/o odt, 144m,288m 36m&72m w/ odt 144m&288m w/o odt, 36m,72m 144m&288m w/ odt burst length = 4 word burst density = 144mb density = 288mb common i/o separate i/o vendor jedec code x18 x9 (11 : 1) ii+ (q dr-ii+, ddr-ii+) ddr qdr with odt without odt r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) package dimensions and marking information both pb parts and pb-free parts are available. hins= 00000.0000.0000.0000.0000 -- - 00000.0000.0000.0000.0000--- 11111.1111 .1111.1111.1111--- 144m jeita package code renesas code previous code mass (typ.) p-lbga165-15x17-1.00 plbg0165fd-a 165fhe 0.6 g reference symbol dimension in mm min nom max d 14.9 15.0 15.1 e 16.9 17.0 17.1 a - - 1.4 a1 0.31 0.36 0.41 [e] - 1.0 - b 0.45 0.5 0.6 x - - 0.2 y - - 0.15 z d - 2.5 - z e - 1.5 - -ys - ?x(m) s ab top view side view bottom view marking information 1st row : vender name (r enesas ) 2nd row: part number 3rd row : y : year code ww : week code xxxx : renesas internal use 4th row : country name (japan) + "none" --- pb -free parts + "pb-f" --- pb-free parts s a1 a z e z d abcdefghjklmnpr 1234567891011 [e] [e] ?b index mark a d index mark (laser mark) b e r1q2a4418rbg-40r ywwxxxx japan pb-f this part number or mark is just one example. r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) hins= 00000.0000.0000.0000.0000 -- - 00000.0000.0000.0000.0000--- 11111.1111 .1111.1111.1111--- 144m revision history (1) 4gx &cvg %qoogpv 4gxe +pkvkcnkuuwg
0gy8gtukqp 4gxc 7rfcvgf6jgtocn4gukuvcpeg 7rfcvgf74.hqt4gpgucu3&454#/*qogrcig 4gxd r10ds0189ej0011
page : ?#? rev. 0.11b : 2012.06.05 r1qba44**rbg / r1qea44**rbg series (preliminary) renesas electronics corporation headquarters: nippon bldg., 2-6-2, ote-machi, chiyoda-ku, tokyo 100-0004, japan notes: 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products f or their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to th e information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the u se of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples . 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circu it examples, is current as of the date this document is issued. such information, however,is subject to change without any prior notice. before purch asing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, ple ase pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website . 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arising out of the uses set forth in the above and purchasers who elect to use rene sas products in any of the foregoing applications shall indemnify and hold harmless renesas electronics corp., its affiliated companies and their of ficers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum ra ting, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characterist ics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to gua rd against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as sa fety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evalu ate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached o r affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas pr oducts may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from ren esas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesa s semiconductor products, or if you have any other inquiries. renesas sales offices http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-6503-0, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 7f, no. 363 fu shing north road taipei, taiwan, r.o.c. tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 --- ? 2012 renesas electronics corporation. all rights reserved. common

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